1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device.
2. Description of the Related Art
In order to realize miniaturization, high density mounting, and so on of a semiconductor device, a stacked multi-chip package in which plural semiconductor elements are stacked and sealed inside of one package is in practical use. In the stacked multi-chip package, the plural semiconductor elements are sequentially stacked via adhesive layers on a wiring substrate. Electrode pads of respective semiconductor elements are electrically connected to an electrode part of the wiring substrate via bonding wires. A multi-layered body as stated above is packaged by a sealing resin, and thereby, the stacked multi-chip package is constituted.
In the stacked multi-chip package, when the same shaped semiconductor elements with each other are stacked or the semiconductor element larger than that of the lower side is stacked at the upper side, there is a possibility that the bonding wire of the lower semiconductor element and the upper semiconductor element may be in contact. Accordingly, it becomes important to prevent occurrences of insulation failure and a short circuit caused by the contact of the bonding wire. Consequently, the following action is taken in which a thickness of the adhesive layer adhering between the semiconductor elements is made to be thick such as 50 μm to 150 μm, and the bonding wire of the lower semiconductor element is taken in the adhesive layer to thereby prevent the contact of the bonding wire with the upper semiconductor element (refer to Japanese Patent Laid-open Application No. JP-A 2001-308262 (KOKAI), Japanese Patent Laid-open Application No. JP-A 2004-072009 (KOKAI)).
A semiconductor wafer is cut in accordance with an element region after an adhesive film and a dicing tape are sequentially laminated on a rear surface of the semiconductor wafer, in order to prepare the sectioned upper semiconductor element. The sectioned semiconductor element is picked up from the dicing tape, and adhered on the lower semiconductor element by using the adhesive film on the rear surface. When a thin semiconductor wafer of which thickness is 85 μm or less is diced, a step cut is applied to suppress a chipping of the semiconductor element (refer to Japanese Patent Laid-open Application No. JP-A 5-074932 (KOKAI)). The step cut is performed by cutting to the dicing tape by a second axis dicing blade after the semiconductor wafer is cut into the middle by a first axis dicing blade.
When an adhesive film having a normal thickness of 10 μm to 25 μm is used, the adhesive film may not have a bad effect on the cut of the semiconductor wafer. However, when a thick adhesive film provided with a spacer function is applied, problems may occur such that the adhesive films is bonded caused by the deformation of adhesive at the time of cutting, the mixture of cut scraps, and cutting heat (approximately 80° C.). This may cause pick up failure of the semiconductor element. Concretely speaking, the adhesive films are bonded to thereby generate breaks and cracks on the semiconductor element at the time of the pick up, or element failure may occur because several pieces of semiconductor elements are picked up continuously.